This invention relates to semiconductor integrated circuit devices including substrate-bias generation circuits.
Recently, there have been proposed various large scale integration (LSI) circuits that include substrate-bias generation circuits. These circuits are intended to reduce the PN junction capacity of diffusion layers for increasing the device operation speed and stabilizing the threshold voltage V.sub.T of metal oxide semiconductor (MOS) transistors.
Also, these circuits are sometimes intended for the purpose of meeting dynamic random access memories (RAM). More particularly, they may be intended to reduce the number of necessary external power sources by replacing the prior art dynamic RAM which is of a type requiring two power sources with one requiring only a single power source.
In the meantime, the current supply capacity of the prior art substrate-bias generation circuit is low, usually of the order of 10 .mu.A. In this case, the substrate is susceptible to external or internal noise, and are prone to potential fluctuations. For example, it has been known that with a dynamic RAM the substrate potential is subject to periodic variations by 1 to 2 V due to such cases as the charging and discharging of an address decoder or a bit line. Such substrate potential fluctuations adversely affect the operation of the LSI and cause malfunction thereof.
FIG. 1 shows a prior art address decoder circuit which is generally used for a dynamic RAM or the like. FIGS. 2A through 2G serve as a timing chart showing potentials at various parts of the circuit of FIG. 1 at the time of an erroneous operation.
The operation of the circuit shown in FIG. 1 will now be described with reference to FIG. 2A through 2G.
In a pre-charge cycle, a pre-charge control signal .phi..sub.p (FIG. 2A) is equal to a power source potential V.sub.DD (for instance 5 V), and nodes N.sub.1 and N.sub.2 are pre-charged (FIGS. 2D and 2E). The pre-charge level is lower than the power source potential V.sub.DD (for instance 5 V) by a threshold voltage V.sub.T of MOS transistors 11 and 12 (for instance about 0.8 V); that is, it is V.sub.DD -V.sub.T (for instance about 4.2 V). When an active cycle sets in with the signal .phi..sub.p reduced to 0 V after the pre-charge cycle has been ended, address signals A.sub.0 (FIG. 2B), A.sub.1, . . . , A.sub.m are coupled to respective MOS transistors 13.sub.1, 13.sub.2, . . . , 13.sub.m. The transistors 13.sub.1 to 13.sub.m are individually on-off operated according to the content of the respective address signals A.sub.0 to A.sub.m. When one of the transistors 13.sub.1 to 13.sub.m is triggered, the nodes N.sub.1 and N.sub.2 are discharged to 0 V through that transistor. When none of the transistors is triggered, the nodes N.sub.1 and N.sub.2 are not discharged, and a floating state at a high level (V.sub.DD -V.sub.T) is maintained. When the circuit serves as a decoder circuit, a non-selected state is obtained with the discharge of the nodes to 0 V, and a selected state corresponds to the nodes not discharged but at the floating level.
If the substrate potential V.sub.BB (FIG. 2G) changes from, for instance, -3 V to -4 V with the discharge of a bit line while the nodes N.sub.1 and N.sub.2 are in a floating state, the potential on the node N.sub.1 is reduced due to a coupling capacitor 14 between the node N.sub.1 and substrate. In the IC device, the node N.sub.1 is formed by a diffusion region. Thus, a high PN junction capacitance is present between the node N.sub.1 and substrate. This PN junction capacitance occupies 79 to 80% of the load capacitance of the node N.sub.1. The potential on the node N.sub.1 is thus reduced from the potential V.sub.DD -V.sub.T (being about 4.2 V) by an amount corresponding to the voltage drop .DELTA.V.sub.BN (for instance 0.7 V) due to a change of the substrate potential to be V.sub.DD -V.sub.T -.DELTA.V.sub.BN (for instance about 3.5 V). As a result, a MOS transistor 12, which has been in the cut-off state or in a high impedance state close thereto owing to the presence of a relation V.sub.G -V.sub.S .ltoreq.V.sub.T between its gate potential V.sub.G and the source potential (potential on the node N.sub.2), is rendered into the "on" state where a relation V.sub.G -V.sub.S &gt;V.sub.T holds or a low impedance state close thereto. Thus, the potential on the node N.sub.2 is reduced to be substantially equal to the potential on the node N.sub.1 (for instance about 3.6 V), that is, the potential level becomes lower than V.sub.DD -V.sub.T.
When a drive signal .phi..sub.d (FIG. 2C) is coupled to a transistor 15 in this state, the potential of the channel under the gate of the transistor 15 is increased substantially in synchronism to the drive signal .phi..sub.d. As a result, the gate potential on the transistor 15 (i.e., the potential on the node N.sub.2) tends to increase due to the coupling capacitance between the gate and channel. However, the rise of the potential on the node N.sub.2 is suppressed by the transistor 12 which is "on" at this time. This means that only a low potential signal (for instance about 2.8 V ) (FIG. 2F), which is the result of subtraction of the threshold potential (for instance 0.8 V) of the transistor 15 from the potential (about 3.6 V) on the node N.sub.2, will appear at an output terminal OUT, that is, the output signal potential will be inevitably low.
In the meantime, in a dynamic RAM, which has its output terminal OUT connected to the gate of a read/write transistor in a memory cell or to the gate of a read/write transistor in a bit line, reliable reading and writing cannot be ensured unless a signal of a sufficient level is obtained from the output terminal OUT. In addition, if the signal level at the output terminal OUT is reduced, the source voltage range of the RAM can no longer cover a sufficiently low potential, which is liable to adversely affect the reliability of the product or the yield of manufacture.